We compared the performance of the designed SFG dual-rail NOR gate with the conventional dual-rail NOR gate. In this paper, we used the SFG concept to speed up the performance of the conventional dual-rail logic. The main aim is to increase the current of the evaluation transistor (EN) to achieve higher speed in the evaluation phase. By applying the input signals, using input capacitors (Cin), to the gate of evaluation transistors (EN), these nodes (SFG nodes) can have a larger voltage level than power supply-voltage (VDD). ULVSFG logic implemented in a modern CMOS process requires frequent initialization (pre-charge) to minimize leakage. SFG technique has been proposed for ULV NP-domino logic structures. Domino CMOS has become a popular logic family for high-performance and high-speed applications and it is extensively used to implement high-speed processors -, since they provide advantages over static-CMOS logic, including fast operation, and lower number of transistors (lower silicon area). Domino logic is known as a high-performance circuit configuration which normally utilizes clocking scheme and is embedded in the static-logic environment.
Hence, operability is the main goal in implementing ULV systems in these high-speed applications. Current digital design techniques do not offer reliable and high-speed logic circuit that can operate at deep sub-threshold voltages. On the other side, the general trend for increasing the operating frequencies and circuit complexity, in the modern high-performance processing applications, requires the design of very innovative high-speed circuits. In one side, increasing the market of low-cost portable-devices demands the design of the low-power blocks that enable the implementation of long-lasting battery-powered systems. Furthermore, existence of substantial leakage current in the modern CMOS nodes prevents the scaling of Vth aggressively. The downscaling of CMOS technology (for higher transistor-density and computing-capacity) and reducing supply-voltage results in degradation in the speed of the logic circuits due to reduced gate-source voltage of the transistors. Sub-threshold design often considered as a very suitable, and energy-efficient solution for these emerging energy-constrained applications. For these ULV applications, often innovative techniques utilized to reduce the overall energy consumption. These ULV systems are extensively used in the modern applications such as low-cost iOT devices, wearable-electronics, intelligent remote sensors, implantable/wearable medical-devices, and energy-harvesting systems. Examples of such power saving techniques include supply-voltage scaling, multi-threshold logic, transistor-stacking, and power-gating.
Tmsc dominos portable#
However, in the modern low-power (LP) and ultra-low-voltage (ULV) portable applications, the energy supply is strictly limited, and the overall system benefits from the innovative techniques for active energy minimization and standby power reduction. For decades, the supply voltage of this system, has been set above the transistor’s threshold voltage (Vth), and called above-threshold (or super-threshold) operation. Traditionally for the high-performance systems, design considerations assume a sufficient and stable supply of energy source to maintain constant performance throughout overall system operation.
Modern electronic technology faces trade-offs between power budget, and performance.
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